Please select a product from the list below:
Available Products:
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54AC273
The 54AC273 consists of eight D-type flip-flops equipped with buffered common Clock (CP) and common Reset (/MR) inputs. A low-to-high edge triggered clock transition loads each flip-flop. Reset is asynchronous and active-low triggered.
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54AC74
Dual D-type flip-flop made in 1.5µm 5V CMOS. Each flip-flop has separate data, set, reset, clock inputs & QQ\ outputs. D-Input level transfers to Q output on positive clock pulse. Set & Reset lines are clock independent, set via high levels.
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54ACT574
The 54ACT574 integrates eight D-type Flip-Flops, a buffered common Clock (CLK) and a buffered common Output Enable (OE). The information presented to the D-type inputs is stored in the flip-flops on the LOW-to-HIGH Clock (CLK) transition.
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54ACT74
Dual D-type flip-flop made in 1.5µm 5V CMOS. Each flip-flop has separate data, set, reset, clock inputs & QQ\ outputs. D-Input level transfers to Q output on positive clock pulse. Set & Reset lines are clock independent, set via high levels.
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54ALS174
Hex D-type flip-flop made using a 2µm 40V Bipolar process. Each flip-flop has separate data inputs & outputs. Load & clear is simultaneous,triggered by common clock & master reset respectively. D-Input transfers to Q output on positive clock pulse.
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54HC174
The 54HC174 consists of six positive edge triggered Hex D-type flip-flops with common clock & master reset inputs. Each D input state is loaded on the positive edge of the clock transition. Reset is asynchronous and active low.
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54HC175
The 54HC175 consists of four positive edge triggered D-type flip-flops with common clock & master reset inputs. Each D input state is loaded on the positive edge of the clock transition. Reset is asynchronous and active low.
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54HC74
Dual D-type flip-flop made in 2.5µm 5V CMOS. Each flip-flop has separate data, set, reset, clock inputs & QQ\ outputs. D-Input level transfers to Q output on positive clock pulse. Set & Reset lines are clock independent, set via high levels.
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74AC273
The 74AC273 consists of eight D-type flip-flops equipped with buffered common Clock (CP) and common Reset (/MR) inputs. A low-to-high edge triggered clock transition loads each flip-flop. Reset is asynchronous and active-low triggered.
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74AC74
Dual D-type flip-flop made in 1.5µm 5V CMOS. Each flip-flop has separate data, set, reset, clock inputs & QQ\ outputs. D-Input level transfers to Q output on positive clock pulse. Set & Reset lines are clock independent, set via high levels.
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74ACT574
The 74ACT574 integrates eight D-type Flip-Flops, a buffered common Clock (CLK) and a buffered common Output Enable (OE). The information presented to the D-type inputs is stored in the flip-flops on the LOW-to-HIGH Clock (CLK) transition.
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74ACT74
Dual D-type flip-flop made in 1.5µm 5V CMOS. Each flip-flop has separate data, set, reset, clock inputs & QQ\ outputs. D-Input level transfers to Q output on positive clock pulse. Set & Reset lines are clock independent, set via high levels.
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74ALS174
Hex D-type flip-flop made using a 2µm 40V Bipolar process. Each flip-flop has separate data inputs & outputs. Load & clear is simultaneous,triggered by common clock & master reset respectively. D-Input transfers to Q output on positive clock pulse.
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74HC174
The 74HC174 consists of six positive edge triggered Hex D-type flip-flops with common clock & master reset inputs. Each D input state is loaded on the positive edge of the clock transition. Reset is asynchronous and active low.
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74HC175
The 74HC175 consists of four positive edge triggered D-type flip-flops with common clock & master reset inputs. Each D input state is loaded on the positive edge of the clock transition. Reset is asynchronous and active low.
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74HC74
Dual D-type flip-flop made in 2.5µm 5V CMOS. Each flip-flop has separate data, set, reset, clock inputs & QQ\ outputs. D-Input level transfers to Q output on positive clock pulse. Set & Reset lines are clock independent, set via high levels.
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CD4013B
Dual D-type flip-flop made in 3µm 15CMOS. Each flip-flop has separate data, set, reset, clock inputs & QQ\ outputs. The D-Input level transfers to Q output on positive clock pulse. Set & Reset lines are clock independent, set via high levels.
