Please select a product from the list below:
Available Products:
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54HC164
54HC164 is an 8–bit, serial–input to parallel–output shift register. x2 serial data inputs are provided so that 1 input may be used as a data enable. Data is entered on the rising clock edge. Asynchronous reset overrides clock & serial data inputs.
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54HC595
The 54HC595 is an 8–bit serial-in to parallel-out shift register driving an 8–bit D–type latch with 3–state outputs. Both register & latch have independent positive triggered clock inputs. The shift register also features asynchronous reset.
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54HC597
The 54HC597 consists of an 8-bit storage register supplying a parallel-in to serial-out 8-bit shift register. Both storage & shift register have positive edge-triggered clocks. The shift register has direct overriding serial load and clear inputs.
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54LS164
54LS164 is an 8–bit, serial–input to parallel–output shift register. x2 serial data inputs are provided so that 1 input may be used as a data enable. Data is entered on the rising clock edge. Asynchronous reset overrides clock & serial data inputs.
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74HC164
74HC164 is an 8–bit, serial–input to parallel–output shift register. x2 serial data inputs are provided so that 1 input may be used as a data enable. Data is entered on the rising clock edge. Asynchronous reset overrides clock & serial data inputs.
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74HC595
The 74HC595 is an 8–bit serial-in to parallel-out shift register driving an 8–bit D–type latch with 3–state outputs. Both register & latch have independent positive triggered clock inputs. The shift register also features asynchronous reset.
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74HC597
The 74HC597 consists of an 8-bit storage register supplying a parallel-in to serial-out 8-bit shift register. Both storage & shift register have positive edge-triggered clocks. The shift register has direct overriding serial load and clear inputs.
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74LS164
74LS164 is an 8–bit, serial–input to parallel–output shift register. x2 serial data inputs are provided so that 1 input may be used as a data enable. Data is entered on the rising clock edge. Asynchronous reset overrides clock & serial data inputs.
